1. Field of the Invention
This invention relates to a mixing prevention circuit which prevents mixing of different semiconductor chips and is used to discriminate a semiconductor chip and a semiconductor chip discrimination method using the mixing prevention circuit.
2. Description of the Related Art
In a process for manufacturing a large-scale semiconductor integrated circuit (which is hereinafter referred to as an LSI), a wafer which has been subjected to a wafer measurement/evaluation process called a die sort test is divided into individual chips in a dicing step. After this, only chips of good quality are set into respective packages in an assembly step.
At this time, chips of different products may sometimes be mixed in a manufacturing process in which chips of normal products (which are hereinafter referred to as normal chips) flow. If the chips thus mixed. (which are hereinafter referred to as mixed chips) are packaged, it becomes difficult to make chip discrimination based on the functions thereof until the final test in a case where normal chips and mixed chips are products with the same function such as general logic products. Therefore, there will occur a problem that different chips are shipped and defects occur in the market.
In the conventional mixing prevention method, normal chips and mixed chips are discriminated based on a difference between the electrical characteristics which can be used in the normal chip and mixed chip by use of a mixing prevention circuit as will be described below. One example of the conventional mixing prevention circuit formed in the chip is shown in FIG. 3 (for example, refer to “TOSHIBA Very High Speed C2MOS TC74VHC-VHCT Series Data Book 1999”, TOSHIBA Corp. Semiconductor Co. p. 83 or “Low Voltage C2MOS Logic TC74VCX/LCX/LVX Series Data Book 2001”, TOSHIBA Corp. Semiconductor Co. p. 871).
Assume that an input signal IN is input to an input terminal TI of the mixing prevention circuit and an output signal OUT is output from an output terminal TO. The mixing prevention circuit is an inverter circuit configured by a first-stage inverter, second-stage inverter and buffer section. The first-stage inverter is configured by transistors TR1, TR2 and supplied with the input signal IN. The second-stage inverter is configured by transistors TR3, TR4 and supplied with an output of the first-stage inverter. The buffer section is configured by transistors TR5, TR6 and supplied with an output of the second-stage inverter.
A “Vin-ICC′ method” is explained below as one example of the conventional mixing prevention method using the mixing prevention circuit.
A D.C. voltage which changes from ground potential GND to power supply voltage VDD is applied to the input terminal TI after preset power supply voltage VDD is applied to the inverter circuit. Then, the transistors TR1, TR2 configuring the first-stage inverter are both set into the ON state so as to permit a penetration current ICC′ to flow from the power supply voltage node VDD to the ground potential node GND via the transistors TR1, TR2. At this time, voltage applied to the input terminal TI is used as input application voltage.
Since a value of the penetration current ICC′ varies according to the input application voltage value, an input application voltage value is set so that penetration currents ICC′ will not be set to the same value in a permissible process fluctuation range between normal chips and mixed chips by using the penetration current ICC′ as an available electrical characteristic difference. With the thus set input application voltage value, since a difference always occurs between the penetration currents ICC′ of the normal chips and mixed chips, discrimination between the normal chip and the mixed chip can be made by applying the input application voltage and measuring the penetration current ICC′.
However, since the value of the penetration current ICC′ is controlled by setting the transistor size of the first-stage inverter in the conventional mixing prevention method, the following problems (1), (2) occur.
(1) When the transistor size of the first-stage inverter is set small, the switching speed is lowered.
(2) When the transistor size of the first-stage inverter is set large, CPD (Power Dissipation Capacitance) is deteriorated.
The above problems (1), (2) will be a cause of deterioration of the product characteristics.
Further, in the conventional mixing prevention method described above, it becomes difficult to detect the electrical characteristic difference because of a process fluctuation such as a variation in the manufacturing process. In addition, it is predicted that the number of products with the same function will increase with shrinkage or a lowering in the voltage, and therefore; it becomes difficult to discriminate semiconductor chips.